On massively parallel devices, traditional debuggers are often inadequate to debug and understand complex interaction of components. Therefore, traces are often the only way to debug and understand programs running on such platforms.
This presentation will provide an overview of trace infrastructure on a Massively Parallel Processor Array (256 cores, 700 Giga operations per second, typical 5W power consumption) including:
- a presentation of the hardware device characteristics
- a presentation of the software framework for tracepoint definition, tracepoint activation, trace generation and acquisition
- a presentation of the trace viewer, based on TMF (the Eclipse Tracing and Monitoring Framework)